The present invention relates generally to integrated circuit devices, and, more particularly, to a method and apparatus for selectively altering dielectric properties of localized regions within an integrated circuit device.
Advancements in the technology of integrated circuits have enabled designers to place relatively large numbers of digital logic gates as an array on a single integrated circuit (IC) chip. As a result, numerous approaches have evolved for interconnecting the logic gates of such high-density, digital logic ICs. A first approach (which may be thought of in terms or a “hard wired” interconnection) uses the fixed layout of various conductive paths in the IC that are either diffused in the substrate or patterned in metallization layers of the IC to interconnect input and output terminals of logic gates, one to the next. As integrated circuit devices have become able to perform more functions within a single integrated circuit chip, the manufacturers of integrated circuit chips have developed ways of automatically and quickly responding to orders for custom chips to perform specific functions for specific applications.
Typically, mask programmed gate array manufacturers apply custom metallization layers as a final step in a standard manufacturing process in order to connect transistors located within a semiconductor substrate to perform a particular logic function ordered by a customer. Manufacturers also provide fully customized integrated circuit devices in which the entire layout of the chip is selected to meet the needs of the customer. An Application Specific Integrated Circuit (ASIC) is a term used in the industry to refer to an integrated circuit device for which the design is completed before manufacturing is completed and the IC is not programmable later. For the customer with a finalized design intended for long term, large volume production, custom metallization or full custom design can be an excellent choice.
On the other hand, for customers that make frequent design changes, desire only small numbers of identical devices, or that may not yet have fully tested a new design and remain in the early stages of a product's life cycle, field programmable integrated circuit chips are an alternative choice. In one form of a field programmable chip, there are several pass transistors that can be turned on or off to connect/not connect corresponding lines to logic circuits, to other lines, or to input/output pads. By turning on a particular combination of pass transistors and connecting a particular set of lines, a user can obtain a desired function. The user can also reprogram a different design into the chip by turning on different combinations of pass transistors. In another form of programmable chip, interconnection of metal lines can be achieved through a field programmable via connection typically known as an antifuse.
The field programmable approach loses its advantage over the mask-defined approach in later phases of a product's life cycle when demand for the product grows, uncertainty about the design disappears, and chips need to be produced in relatively large volumes (e.g., 10,000 units or more). The total cost of the chip at such a point in its life cycle tends to be greater when the chip is a field programmable logic device (FPLD) rather than a mask-defined chip. One reason field programmable chips have a larger overall cost is that the memory cells and pass transistors in field programmable chips consume large amounts of space compared to the simple metal process used in mask-defined chips.
In addition, software design tools are also used to simplify the process of programming a FPLD by executing a wide variety of tasks such as analysis and minimization of circuit designs, determining if a circuit design can be implemented by a target FPLD, partitioning a circuit design into logic functions which can be implemented by a target FPLD, selecting which circuit design logic function is implemented by which FPLD logic function, determining connections of FPLD interconnect resources necessary to implement the circuit design logic, providing performance information and generating a set of commands for automatic configuration of FPLDs using a device programmer. A circuit design may be first converted into a computer readable form using a hardware description language, or using a schematic capture program. Typical software design tools then perform a “logic optimization” process that includes minimizing the number of logic elements necessary to provide the logic functions defined by the circuit design. Next, typical software design tools perform “technology mapping” in which logic of the circuit design is divided into component logic functions. These component logic functions are then compared to and matched with logic functions implemented by a target FPLD. Because the different FPLDs can implement different logic functions, technology mapping of a circuit design must be performed for each target FPLD. After technology mapping is complete, placement and routing are performed and a bit stream is typically generated which represents the programmed states of all of the programmable components of the target FPLD.
Accordingly, a desirable alternative to conventional field programmable devices programmed through somewhat complex and time consuming software processes would be the ability to externally customize a packaged integrated circuit device by directly changing certain physical characteristics of the device, such as, for example, the dielectric constant of an insulating layer(s) therein.